1. Field of the Invention
This invention relates to plasma etching of platinum. More specifically, this invention provides a method for plasma etching of platinum for producing semiconductor integrated circuits containing platinum electrodes.
2. Description of the Prior Art
The implementation of digital information storage and retrieval is a common application of modern digital electronics. Memory size and access time serve as a measure of progress in computer technology. Quite often storage capacitors are employed as memory array elements As the state of the art has advanced, small-feature-size high density dynamic random access memory (DRAM) devices require storage capacitors of larger capacitance having high dielectric constant materials. The high dielectric constant materials or ferroelectric materials are made primarily of sintered metal oxide and contain a substantial amount of very reactive oxygen. In the formation of capacitors with such ferroelectric materials or films, the electrodes must be composed of materials with least reactivity to prevent oxidation of the electrodes which would decrease the capacitance of storage capacitors. Therefore, precious metals, such as platinum (Pt), palladium (Pd), etc., are preferred metals used in the manufacture of capacitors for high density DRAM.
Among the possible precious metals for capacitor electrodes, platinum has emerged as an attractive candidate because it is inert to oxidation and is known to have a leakage current ( less than 10xe2x88x929 amps/cm2) lower than other electrodes such as Ru02 and Pd. Platinum also is a good conductor.
In the prior art, platinum etching has been conducted by means of isotropic etching, such as wet etching with aqua regia, or by anisotropic etching, such as ion milling with Ar gas or by other means. Because of the nature of isotropic etching, using wet etching with aqua regia causes deteriorated processing accuracy. The grade of precision in isotropic etching is not high enough for fine pattern processing. Therefore, it is difficult to perform submicron patterning of platinum electrodes due to its isotropic property. Furthermore, a problem with ion milling (i.e. anisotropic etching) occurs because the etching speed on platinum, which is to form the electrode, is too slow for mass production.
In order to increase processing accuracy in etching platinum, research and development has been quite active, particularly in the area of etching platinum by means of a dry etching process where etchant gases (e.g., Cl2, HBr, O2, etc.) are used. The following prior art is representative of the state of art with respect to etching platinum with a plasma of etching gases.
U.S. Pat. No. 5,492,855 to Matsumoto et al. discloses a semiconductor device manufacturing method, wherein an insulation layer, a bottom electrode Pt layer, a dielectric film and a top electrode Pt layer are provided on top of a substrate having already-completed circuit elements and wiring, and then, a capacitor is formed by selectively dry etching the bottom electrode Pt layer after selectively dry etching the top electrode Pt layer and the dielectric film. The manufacturing method uses a gas containing an S component as etching gas for Pt etching, or an etching gas containing S component as an additive gas; and also it implants S into the Pt layer before the Pt dry etching process by means of ion implantation to compose a S and Pt compound, and then dry etches the Pt compound thus composed.
U.S. Pat. No. 5,527,729 to Matsumoto et al. discloses process steps to form on a substrate in which circuit elements and wirings, etc., are already shaped, an insulation layer, a first metal layer, a dielectric film and a second metal layer. A top electrode and a capacitance film are formed by dry etching the second metal layer and the dielectric film. A bottom electrode is formed by dry etching the first metal layer. The etching gas for dry etching the second metal layer is a mixed gas containing hydrogen halide (e.g. HBr) and oxygen, having a ratio of oxygen against the total of hydrogen halide and oxygen set at about 10%-35%. The etching gas is also taught as a gas containing hydrocarbon, such as chloroform. Matsumoto et al. employs a silicon oxide layer as the insulation layer on the substrate, and a platinum layer or palladium layer as the first and second metal layers. Dry etching of the second metal layer and dielectric film is conducted in a low pressure region not higher than about 5 Pa, where the etching speed is high. Matsumoto et al. further teaches that where a mixed gas of hydrogen halide and oxygen is used as the etching gas, the etching speed on the silicon oxide layer can be made sufficiently low relative to that on the second metal layer made of a platinum layer or a palladium layer; in this way, the excessive etching of the silicon oxide layer underlying the first metal layer is avoided, and damage to the circuit elements and wiring, etc. underneath the silicon oxide layer can be prevented. Furthermore according to Matsumoto et al, the ratio of etching speed of the platinum and dielectric material to the resist can be increased by lowering the etching speed on the resist. Therefore, etching of the platinum and dielectric material may be conducted by using a mask of normal lay-thickness resist (generally speaking, about 1.2 xcexcm to about 2.0 xcexcm thick), instead of using a conventional thick-layer resist (about 3 xcexcm and thicker).
Chou et al. in an article entitled xe2x80x9cPlatinum Metal Etching in a Microwave Oxygen Plasmaxe2x80x9d, J. Appl. Phys. 68 (5), Sep. 1, 1990, pages 2415-2423, discloses a study to understand the etching of metals in both plasma and chemical systems. The study found that the etching of platinum foils in an oxygen plasma generated in a flow-type microwave system and that very rapid etching (xcx9c6 xc3x85/s) took place even at low power inputs (200 W). The principal plasma parameters, including oxygen atom concentration, ion concentration, and electron temperature, were measured by Chou et al. as a function of distance below the microwave coupler. These were correlated to the rate of foil etching, which decreased with increasing distance from the coupler. On the basis of these correlations Chou et al. formulated a simple mechanistic model. The study by Chou et al. further found that the etching of platinum in an oxygen plasma jet results from the concomitant action of oxygen atoms and high energy electrons.
Nishikawa et al. in an article entitled xe2x80x9cPlatinum Etching and Plasma Characteristics in RF Magnetron and Electron Cyclotron Resonance Plasmasxe2x80x9d, Jpn. J. Appl. Phys., Vol. 34 (1995), pages 767-770, discloses a study wherein the properties of platinum etching were investigated using both rf magnetron and electron cyclotron resonance (ECR) plasmas, together with measurement of the plasma parameters (neutral concentration, plasma density, etc.). Nishikawa et al. performed experiments in Cl2 plasmas over a pressure ranging from 0.4 to 50 mTorr. In rf magnetron plasmas, the etch rate of Pt was constant at the substrate temperature of from 20 to 160xc2x0 C. The etch rate and the plasma electron density increased with gas pressure decreasing from 50 to 5 mTorr. In ECR plasmas for rf power of 300 W, Nishikawa et al. found that the etch rate of Pt was almost constant (xcx9c100 nm/min) with gas pressure decreasing from 5 to 0.4 mTorr, while the plasma electron density gradually increased with decreasing gas pressure. The study by Nishikawa et al. discusses these experimental results with respect to the relationship between the etch yield and the ratio of neutral Cl2 flux and ion flux incident on the substrate.
Yokoyama et al. in an article entitled xe2x80x9cHigh-Temperature Etching of PZT/Pt/TiN Structure by High-Density ECR Plasmaxe2x80x9d, Jpn. J. Appl. Phys., Vol. 34 (1995), pages 767-770, discloses a study wherein micron patterning technologies for the PZT/Pt/TiN/Ti structure with a spin on glass (SOG) mask are demonstrated using a high-density electron cyclotron resonance (ECR) plasma and a high substrate temperature above 300xc2x0 C. A 30%-Cl2/Ar gas was used to etch a lead zirconate titanate (PZT) film. No deposits remained, which resulted in an etched profile of more than 80xc2x0. A 40%-O2/Cl2 gas was used to etch a Pt film. The etching was completely stopped at the Ti layer. 30-nm-thick deposits remained on the sidewall. They were removed by Yokoyama et al. after dipping in hydrochloric acid. The etched profile of a Pt film was more than 80xc2x0. The Ti/TiN/Ti layer was etched with pure Cl2 gas. The size shift from the SOG mask was less than 0.1 xcexcm. Yokoyama et al. did not detect any interdiffusion between SOG and PZT by transmission electron microscopy and energy dispersive x-ray spectroscopy (TEM-EDX) analysis.
Yoo et al. in an article entitled xe2x80x9cControl of Etch Slope During Etching of Pt in Ar/Cl2/O2 Plasmasxe2x80x9d, Jpn. J. Appl. Phys., Vol. 35 (1996), pages 2501-2504, teaches etching of Pt patterns of the 0.25 xcexcm design rule at 20xc2x0 C. using a magnetically enhanced reactive ion etcher (MERIE). Yoo et al. found that a major problem of etching with a MERIE was the redeposition of the etch products onto the pattern sidewall, making it difficult to reduce the pattern size. In both cases separately using:a photoresist mask and an oxide mask, the redeposits of the etch products onto the sidewall were reduced by the addition of Cl2 to Ar, although the etched slope was lowered to 45xc2x0. The redeposits were removed by an HCl cleaning process.
Kotecki in an article entitled xe2x80x9cHigh-K Dielectric Materials for DRAM Capacitorsxe2x80x9d, Semiconductor International, November 1996, pages 109-116, the potential advantages of incorporating high-dielectric materials into a storage capacitor of a dynamic random access memory (DRAM) are described and the requirements of the high dielectric layer are reviewed as they relate to use in a simple stack capacitor structure suitable for the gigabit generation. Kotecki teaches that when considering the use of high-dielectric materials in a stack capacitor structure, the following issues need to be addressed: electrode patterning, high-dielectric material/barrier interaction, electrode/high-dielectric material interaction, surface roughness (e.g. hilocking, etc.), step coverage, high-dielectric material uniformity (e.g. thickness, composition, grain size/orientation, etc.), and barrier (e.g. O2 and Si diffusion, conductivity, contact resistance and interactions, etc.). Various materials and combinations of materials were studied by Kotecki for use with perovskite dielectrics including the noble metals (i.e. Pt, Ir, Pd) and conductive metal oxides (i.e. IrO2 and RuO2). The work function of these materials, their ability to be patterned by dry etching, the stability of the surface with regards to surface roughening and their suitability in a semiconductor fabricator are listed by Kotecki in the following Table I:
Kotecki further teaches in the article entitled xe2x80x9cHigh-K Dielectric Materials for DRAM Capacitorsxe2x80x9d that one of the major problems which needs to be overcome with respect to the manufacturing of DRAM chips using capacitors is the problem of electrode patterning. There are minimal volatile species produced during the dry etching of the noble metal electrodes such as Pt, Ru, Pd and Ir. Since the etch mechanism is primarily by physical sputtering, even during a RIE process, fences are typically formed on the sides of the photoresist. To eliminate the problem of fencing, it is possible to etch the fence layer and erode the sides of the photoresist during the etch process which leads to xe2x80x9ccleanxe2x80x9d metal structures but with sloping sidewall angles and a loss of control over critical feature sizes. As the dimension of the feature shrinks to 0.18 xcexcm or below, only limited tapering of the sidewall angle can be tolerated. Kotecki presents in the following Table II some of the high-dielectric materials which have been considered for use in a DRAM capacitor, the various methods which can be used to form the films, and the range of reported permittivites:
Milkove et al. reported in a paper entitled xe2x80x9cNew Insight into the Reactive Ion Etching of Fence-Free Patterned Platinum Structuresxe2x80x9d at the 43rd Symposium of AVS, October 1996, Philadelphia, Pa., that an investigation was undertaken to characterize the time progression of the Pt etch process during the reactive ion etching (RIE) of fence-free patterned structures. The experiment by Milkove et al. consisted of coprocessing two oxidized Si wafers possessing identical 2500 xc3x85 thick Pt film layers, but different photoresist (PR) mask thicknesses. Etching was suspended at 20, 40, 60 and 80% of the full etch process in order to cleave off small pieces of wafer for analysis by a scanning electron microscopy (SEM). Using Cl2-based RIE conditions known to produce fence-free etching for 2500 xc3x85 thick film layers, Milkove et al. discovered that a severe fence actually coats the PR mask during the first 20% of the etch process. As the etch continues the fence structure evolves, achieving a maximum height and width followed by progressive recession until disappearing completely prior to process endpoint. The data from Milkove et al. shows that the final profile of an etched Pt structure possess a functional dependence on the initial thickness and slope of the PR mask, as well as on the initial thickness of the Pt layer. Milkove et al. further reported in the paper entitled xe2x80x9cNew Insight Into The Reactive Ion Etching of Fence-free Patterned Platinum Structuresxe2x80x9d that the observed behavior of the transient fence provides the strongest evidence to date supporting the existence of a chemically assisted physical sputtering component associated with the RIE of Pt films in halogen-based plasmas.
Keil et al. teaches in an article entitled xe2x80x9cThe Etching of Platinum Electrodes for PZT Based Ferroelectric Devicesxe2x80x9d, Electrochemical Society Proceedings, Vol. 96-12 (1996), pages 515-520, that the technical difficulties of fabricating capacitors employing platinum Pt etching is most often dominated by sputtering processes. While oxygen and/or various gaseous chlorides or fluorides are used to chemically enhance the etch process, the products of both etch mechanisms are usually of low volatility and tend to redeposit on the wafer. After etching, large wall-like structures extend up from the edges of the Pt region. These wall-like structures are frequently referred to as xe2x80x9cveilsxe2x80x9d or xe2x80x9cfencesxe2x80x9d or xe2x80x9crabbit earsxe2x80x9d and can reach lengths which are more than double the thickness of the Pt film to which they are attached. The existence of such structures makes useful deposition of the PZT layer impossible. Keil et al. further teaches that even when one is able to attenuate redeposition to the point where only small xe2x80x9cnubxe2x80x9d like features are present, the high electric fields which will form at such xe2x80x9cnubsxe2x80x9d enhances the likelihood for dielectric breakdown. Although process conditions can be found which result in either low redeposition or even no redeposition, they most often also give an unacceptably tapered platinum profile angle. Keil et al. observed that redeposition becomes more severe as process conditions are pushed toward those which give increasingly vertical sidewalls. While a post etch wet clean in a solvent bath is frequently used, the heavy redeposition which attends the pursuit of vertical sidewalls regularly renders this approach minimally effective.
The foregoing prior art illustrates that generally a clean vertical dense area profile and CD (critical dimension) control of the etch profiles are critical factors for successful plasma etching of 1-Gbit (and beyond) DRAM ferroelectric devices possessing platinum electrodes. Redeposition and profile control are found to be strongly interlinked. Optimization of both profile angle and redeposition requires a tradeoff between the two. Where as vigorous post etch cleaning (e.g. wet cleaning with acid, mechanical polishing, etc.) can relieve some of the need to achieve a deposition free plasma etch, such post etch cleaning does not possess the accuracy that is desired as the platinum electrode itself is typically eroded and/or deteriorated by currently known post etch cleaning methods.
Therefore, what is needed and what has been invented is a method for etching a platinum electrode layer to produce a high density integrated circuit semiconductor device having platinum electrodes with a high degree (i.e., xe2x89xa785xc2x0) of platinum profile anisotropy. What is further needed and what has been invented is a semiconductor device including a plurality of platinum electrodes having a platinum profile equal to or greater than about 85xc2x0 and separated by a distance equal to or less than about 0.3 xcexcm with each electrode having a critical dimension (e.g., a width) equal to or less than about 0.3 xcexcm.
The present invention accomplishes its desired objects by broadly providing a method of etching a platinum layer disposed on a substrate comprising the steps of:
a) providing a substrate supporting a platinum layer;
b) heating the substrate of step (a) to a temperature greater than about 150xc2x0 C.; and
c) etching the platinum layer including employing a high density plasma of an etchant gas comprising a halogen containing gas (e.g., a halogen such as chlorine) and a noble gas (e.g., argon) to produce the substrate supporting at least one etched platinum layer.
The platinum layer is preferably a platinum electrode layer. The high density plasma of an etchant gas is a plasma of an etchant gas having an ion density greater than about 109/cm3, preferably greater than about 1011/cm3. The etchant gas may also include a gas selected from the group consisting of BCl3, HBr, and mixtures thereof. The platinum layer of step (a) above may additionally comprise a mask layer disposed on a selected part of the platinum layer to selectively protect the platinum layer during the etching step (c) above. The platinum layer of step (a) may also additionally comprise a protective layer disposed on the selected part of the platinum layer between the mask layer and the platinum layer. The mask layer may be removed during or after the etching step (c). Similarly, the protective layer may be removed during or after the etching step (c). The platinum layer is part of or is contained in a platinum wafer, and the method of etching a platinum layer additionally comprises disposing the platinum wafer including the platinum layer of step (a) in a high density plasma chamber having a coil inductor and a wafer pedestal; and performing the etching step (c) in the high density plasma chamber under the following process conditions:
The etched platinum layer includes a platinum profile equal to or greater than about 85xc2x0, more preferably equal to or greater than about 87xc2x0, most preferably equal to or greater than about 88.5xc2x0. The etchant gas for the process conditions immediately above may alternatively comprise from about 10% to about 90% by vol. of a halogen (e.g., Cl2), from about 5% to about 80% by vol. of a noble gas (e.g., argon), and from about 4% to about 25% by vol. HBr and/or BCl3.
The present invention also accomplishes its desired objects by broadly providing a method for producing a capacitance structure including a platinum electrode comprising the steps of:
a) providing a substrate supporting a platinum electrode layer and at least one mask layer disposed on a selected part of said platinum electrode layer;
b) heating the substrate of step (a) to a temperature greater than about 150xc2x0 C.; and
c) etching the platinum electrode layer including employing a plasma of an etchant gas comprising a halogen (e.g., chlorine) and a noble gas (e.g., argon) to produce a capacitance structure having at least one platinum electrode.
The at least one mask layer is removed during or after the etching step (c) immediately above. The platinum electrode layer of step (a) immediately above may additionally comprise a protective layer disposed on the selected part of platinum electrode layer between the mask layer and the platinum electrode layer. The etched platinum electrode layer produced by the etching step (c) immediately above includes a platinum profile equal to or greater than about 85xc2x0, more preferably equal to or greater than about 87xc2x0, most preferably equal to or greater than about 88.5xc2x0. The etchant gas of the plasma of step (c) more specifically includes a halogen (e.g., chlorine), a noble gas (e.g., argon), and a gas selected from the group consisting of HBr, BCl3 and mixtures thereof. The platinum electrode layer is part of or is contained in a platinum electrode wafer, and the method for producing a capacitance structure including a platinum electrode layer additionally comprises disposing, prior to the etching step (c), the platinum electrode wafer in a high density plasma chamber having a coil inductor and a wafer pedestal; and performing the etching step (c) in the high density plasma chamber under the following previously indicated process conditions:
The produced platinum electrodes are separated by a distance or space having a dimension equal to or less than about 0.3 xcexcm. Each of the platinum electrodes include a dimension having a value equal to or less than about 0.6 xcexcm, preferably equal to or less than about 0.3 1 xcexcm. More preferably, each of the platinum electrodes have a width equal to or less than about 0.3 xcexcm, a length equal to or less than about 0.6 xcexcm, and a height equal to or less than about 0.6 xcexcm. The plasma of the etchant gas comprises a high density inductively coupled plasma. The etchant gas preferably comprises a noble gas selected from the group consisting of helium, neon, argon, krypton, xenon, radon, and mixtures thereof. More preferably, the noble gas is selected from the group consisting of helium, neon, argon, and mixtures thereof. Most preferably, the noble gas is argon. As was previously indicated, the etchant gas of the high density inductively coupled plasma most preferably comprises, or preferably consists of or consists essentially of, chlorine, argon, and BCl3 and/or HBr.
The present invention further accomplishes its desired objects by broadly providing a method of manufacturing a semiconductor device comprising the steps of:
a) forming a patterned resist layer, a mask layer and a platinum electrode layer on a substrate having circuit elements formed thereon;
b) etching a portion of the mask layer including employing a plasma of an etchant gas to break through and to remove the portion of the mask layer from the platinum electrode layer to produce the substrate supporting the patterned resist layer, a residual mask layer, and the platinum electrode layer;
c) removing the resist layer of step (b) to produce the substrate supporting the residual mask layer and the platinum electrode layer;
d) heating the substrate of step (c) to a temperature greater than about 150xc2x0 C.; and
e) etching the platinum electrode layer of step (d) including employing a high density plasma of an etchant gas comprising a halogen gas (e.g., chlorine) and a noble gas (e.g., argon) to produce a semiconductor device having at least one platinum electrode.
The present invention also further accomplishes its desired objects by broadly providing a method of etching a platinum electrode layer disposed on a substrate comprising the steps of:
a) providing a substrate supporting a platinum electrode layer, a protective layer on the platinum electrode layer, and a mask layer on the protective layer, and a patterned resist layer on the mask layer;
b) etching a portion of the mask layer including employing a plasma of an etchant gas to break through and to remove the portion of the mask layer from the protective layer to expose part of the protective layer and to produce the substrate supporting the platinum electrode, layer, the protective layer on the platinum electrode layer, a residual mask layer on the platinum electrode layer, and the patterned resist layer on the residual mask layer;
c) removing the patterned resist layer from the residual mask layer of step (b) to produce the substrate supporting the platinum electrode layer, the protective layer on the platinum electrode layer, and the residual mask layer on the protective layer;
d) heating the substrate of step (c) to a temperature greater than about 150xc2x0 C.;
e) etching the exposed part of the protective layer to expose part of the platinum electrode layer and to produce the substrate supporting the platinum electrode layer, a residual protective layer on the platinum electrode layer, and the residual mask layer on the residual protective layer; and
f) etching the exposed part of the platinum electrode layer of step (e) including employing a high density plasma of an etchant gas comprising a halogen gas (e.g., chlorine) and a noble gas (e.g., argon) to produce the substrate supporting an etched platinum electrode layer having the residual protective layer on the etched platinum electrode layer, and the residual mask layer on the residual protective layer.
The patterned resist layer is removed from the residual mask layer before heating the substrate to a temperature greater than about 150xc2x0 C. because such high temperatures would destroy the resist layer. The residual mask layer may be removed from the platinum electrode layer either before or after heating of the substrate to a temperature greater than about 150xc2x0 C., and during or after the platinum etching step. The platinum electrode layer is part of or is contained in a platinum electrode wafer. The purpose of the protective layer is to ensure the adhesion between the mask layer and the platinum layer and also to maintain the platinum profile of the platinum electrode layer, especially during the platinum etching process of the present invention. Preferably, the residual protective layers are removed from the etched platinum electrodes after the platinum etching step.
As previously indicated, etching of the platinum electrode layer to produce the platinum electrodes of the present invention is performed in a high density plasma chamber. The platinum etching step employs a high density plasma of an etchant gas preferably consisting of, or consisting essentially of, a halogen gas (e.g., chlorine), a noble gas (i.e., argon) and HBr and/or BCl3. The high density plasma chamber possesses a separate control for ion flux and a separate control for ion energy. As previously indicated, the ion density of the high density plasma in the high density plasma chamber is greater than about 109/cm3.
The high density plasma chamber for the method of manufacturing a semiconductor device and for the method of etching a platinum electrode layer disposed on a substrate includes a coil inductor and a wafer pedestal; and the platinum etching step in both of the methods is performed in the high density plasma chamber under the following previously mentioned process conditions:
The present invention yet also further accomplishes its desired objects by broadly providing a semiconductor device, more specifically a capacitance structure, comprising a substrate, and at least two platinum electrodes supported by the substrate. The platinum electrodes have a platinum profile equal to or greater than about 85xc2x0, preferably equal to or greater than about 87xc2x0, more preferably equal to or greater than about 88.5xc2x0. The platinum electrodes are separated by a distance or space having a dimension equal to or less than about 0.3 xcexcm. Each of the platinum electrodes include a dimension having a value equal to or less than about 0.6 xcexcm, preferably equal to or less than about 0.3 xcexcm. More preferably, each of the platinum electrodes have a width equal to or less than about 0.3 xcexcm, a length equal to or less than about 0.6 xcexcm, and a height equal to or less than about 0.6 xcexcm.
It is therefore an object of the present invention to provide a method for etching a platinum layer disposed on a substrate.
It is another object of the present invention to provide a method of manufacturing a semiconductor device.
It is also another object of the present invention to provide a method of manufacturing a capacitance structure.
It is yet another object of the present invention to provide a capacitance structure.
It is also yet another object of the present invention to provide a semiconductor device.
These, together with the various ancillary objects and features which will become apparent to those skilled in the art as the following description proceeds, are attained by these novel methods, and semiconductor devices, a preferred embodiment thereof shown with reference to the accompanying drawings, by way of example only, wherein: